As products such as video cameras and cell phones become smaller and smaller, the electronics industry is increasingly requiring increased miniaturization of integrated circuit packages. At the same time, higher performance and lower cost have become essential for new products.
Semiconductor devices are constructed from a silicon (Si) or gallium-arsenide (Ga/As) wafer through a process that comprises a number of deposition, masking, diffusion, etching, and implanting steps. Usually, many individual devices are constructed on the same wafer. When the devices are separated into individual groups of units, each takes the form of an integrated circuit die.
In order to interface a die with other circuitry, the dies are commonly mounted on a substrate that is surrounded by a number of lead fingers. Each die has bonding pads that are then individually connected in a wire bonding operation to the lead fingers and the assemblies are then packaged by individually encapsulating them in molded plastic, epoxy, or ceramic bodies. The lead fingers of the packages are then processed for attachment to a printed circuit board.
One type of package is the quad flat no lead (QFN) package. The QFN package has the die adhesively bonded to a lead paddle which, along with the lead fingers, is exposed. The QFN package has good electrical and thermal characteristics, however, to increase the number of input/outputs (I/O) for a given body size, it is necessary to reduce the width of the lead fingers and/or insert more rows of lead fingers. However, when the width of the lead fingers is decreased, handling problems are encountered during manufacturing.
Another type of package is the plastic land grid array (PLGA) in which a die is bonded to a paddle and the paddle is bonded to a substrate. The substrate has patterned metal on both sides and through vias connecting the patterned metal. The PLGA package is able to provide relatively high numbers of I/Os for a given body size over a QFN package. However, a liquid photoimageable (LPI) solder mask must be applied on both sides of the substrate exposing only the bonding areas. Adhesion between the LPI solder mask on large metal surfaces is poor, and the packages consistently have problems passing inspection, especially with regard to moisture resistance. In addition, solder mask registration and resolution cause problems because they affect bonding pad size. Further, there is a higher possibility of warpage in the event that solder mask volume or thickness between the top and the bottom is not balanced. In addition, the solder mask layer increases the thermal resistance from the chip to the printed circuit board resulting in inferior thermal dissipation compared to the QFN package.
Further, the PLGA package requires off-set vias requiring a connection between the via and the land.
Solutions to these problems have long been sought, but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.